[L2Ork-dev] dsp chain indeterminism

[Jonathan Wilkes]

Ah yeah, nevermind.  I forgot about the phase. So:

1. frequency is 440
2. a connection is made to [sig~ 0]
3. whatever the phase happened to be at the time of the connection is
applied to frequency 0

I guess the phase could be reset to zero at graph-building time. On
the other hand, people
do such odd things with dynamic patching-- who knows if this would
break some of that
insanity.

-Jonathan

On Mon, Jun 25, 2018 at 3:55 PM, Matt Barber <brbrofsvl at gmail.com> wrote:
> There are also ways of noticing when a connection is attached to the inlet
> and that the connection is a signal, and you can reset phase at those times
> instead.
>
> On Mon, Jun 25, 2018 at 3:52 PM Matt Barber <brbrofsvl at gmail.com> wrote:
>>
>> Only good way to do this is to reset phase when the dsp graph changes.
>> [cyclone/cycle~] does this, in fact:
>>
>> static void cycle_dsp(t_cycle *x, t_signal **sp)
>>   cycle_gettable(x);
>>     x->x_conv = 1.0 / sp[0]->s_sr;
>>     cycle_phase_reset(x); // <------------------------------RESET PHASE
>>     dsp_add(cycle_perform, 5, x, sp[0]->s_n,
>>     sp[0]->s_vec, sp[1]->s_vec, sp[2]->s_vec);
>> }
>>
>> On Mon, Jun 25, 2018 at 3:40 PM Jonathan Wilkes <jon.w.wilkes at gmail.com>
>> wrote:
>>>
>>> Hi list,
>>>
>>> Check out the following patch (attached):
>>>
>>> 1. Click [bang(. You'll get a block of ones.
>>>
>>> 2. Disconnect the output of [sig~ 0] from the input of [osc~ 440].
>>>
>>> 3. Click the [bang( again. You'll get output based on the floatarg 440.
>>>
>>> 4. Now re-connect [sig~ 0] to [osc~ 440]. You'll get indeterministic
>>> output.
>>>
>>> Is there any workaround to make the output deterministic in this case?
>>>
>>> -Jonathan
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>
>
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